VHDL - Somador de 4 bits - Xilinx

https://www.youtube.com/watch?v=wB5E3IgtKIw

Dois exemplos de somadores de 4 bits na linguagem VHDL utilizando o Xilinx:

1 - Somador 4 bits Simples - Nome: somador4bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_signed.all;

entity somador4bits_1 is
PORT ( a, b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR (4 DOWNTO 0));
end somador4bits_1;

architecture Behavioral of somador4bits_1 is

begin
s <= a + b;
end Behavioral;

2 - Somador 4 bits Recursivo - É necessário criar dois New Source para o mesmo projeto.

2.1 Nome: somador1bit

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity somador1bit is

PORT (cin, a, b : IN STD_LOGIC;
s, cout : OUT STD_LOGIC);

end somador1bit;

architecture Behavioral of somador1bit is

begin

s <= a XOR b XOR cin;
cout <= (a AND b) OR (a AND cin) OR (b AND cin);

end Behavioral;

2.2 Nome: somador4bits

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity somador4bits is

PORT (c0, a3, a2, a1, a0, b3, b2, b1, b0 : IN STD_LOGIC;
s3, s2, s1, s0, c4 : OUT STD_LOGIC);

end somador4bits;

https://www.youtube.com/watch?v=wB5E3IgtKIw

architecture Behavioral of somador4bits is

SIGNAL c1, c2, c3: STD_LOGIC;

COMPONENT somador1bit

PORT (cin, a, b : IN STD_LOGIC;
s, cout : OUT STD_LOGIC);

END COMPONENT;

begin

SC0: somador1bit PORT MAP (c0, a0, b0, s0, c1);
SC1: somador1bit PORT MAP (c1, a1, b1, s1, c2);
SC2: somador1bit PORT MAP (c2, a2, b2, s2, c3);
SC3: somador1bit PORT MAP (c3, a3, b3, s3, c4);

end Behavioral;

https://www.youtube.com/watch?v=wB5E3IgtKIw